It becomes a trend to design a semiconductor memory device having high capacity and high operational speed. Furthermore, it is noticed that a memory device is designed to operate at low voltage or low power to acquire reliable performance at the low power environment. In particular, it is a trend to design a memory device employed in a portable system such as a mobile phone, a notebook computer, etc. to consume the minimum power if possible.
One of the efforts is a technology of reducing current consumption at a core area of a memory device to the minimum. The core area including memory cells, bit lines and word lines is designed according to an extremely delicate design-rule. As a result, the memory cell has a very small size and consumes low power.
A dynamic random access memory (DRAM) widely used in this world employs a bit line precharge operation therein. The bit line precharge operation is to precharge bit lines with a certain voltage value corresponding to an input voltage level of sense amplifiers that judge logical states of data stored in the DRAM, and is performed before a data reading or writing operation. A charged voltage of a cell capacitor in the memory cell corresponding to a logical value “1” is referred to as VCORE and a precharge voltage becomes a half of VCORE.
Referring to FIG. 1, there is shown one example block diagram of a core area in a conventional DRAM device.
The conventional DRAM device includes a cell array 21, a word line (WL) driver 26, a bit line precharge unit 23, a bit line sense amplifying block 22, an input-output block 27, a sense amplifier (SA) controller 24, an equalizer 25, a boosted voltage generator 12 and an equalization signal (BLEQ) driver 16.
In a low power memory device, a storage voltage VCORE of a cell array has a higher level than a supply voltage VDD provided from the outside of the memory device. Moreover, since switches existing at several places in the memory device having cell transistors are mostly formed with MOS transistors, there exists the voltage loss due to gate voltage drop (Vt) of the MOS transistors. Therefore, in order to charge memory cell capacitors with full VCORE by providing a voltage higher than (VCORE+Vt) to gates of cell transistors, a substantially higher voltage than (VCORE+Vt) should be coupled to bit lines. This voltage is generated by pumping the supply voltage VDD and called as a boosted voltage VPP. The memory device includes a boosted voltage generator to produce the boosted voltage VPP.
As described in FIG. 1, in the conventional memory device, the boosted voltage VPP outputted from the boosted voltage generator 12 is provided to the word line (WL) driver 26 and the sense amplifier (SA) controller 24. The boosted voltage VPP is also inputted to the equalization signal (BLEQ) driver 16 as the equalization signal (BLEQ) output voltage.
Using the boosted voltage VPP as the equalization signal BLEQ is called a VPP driving scheme (boosted voltage driving scheme). However, when using this scheme, the driving performance of the boosted voltage VPP may be substantially deteriorated in a range of an operational voltage being lower than 2.0V. In particular, this phenomenon becomes more serious in the low power environment.
In order to generate the boosted voltage VPP having 3.6V from the supply voltage of conventional 2.5V or 3.3V, it is enough to pump 50% or 10% of the supply voltage. That is, one time pumping is sufficient to get the boosted voltage VPP of 3.6V. On the other hand, in order to produce the boosted voltage VPP of 3.6V from the supply voltage of 1.5V or 1.8V, there is required more than 100% voltage pumping of the supply voltage VDD. This is achieved by twice voltage pumping. As a result, the driving performance of the boosted voltage is substantially deteriorated.
In addition, when driving transistors to be switched during a bit line precharge operation by using the boosted voltage, a voltage level of the boosted voltage VPP becomes dropped. If the voltage level of the boosted voltage VPP is dropped, the bit line precharging speed is delayed. Furthermore, word line enablement performed by the boosted voltage VPP is also delayed or there may occur a problem in a refresh operation due to the voltage level down. Also, current consumption increases by driving the boosted voltage generator so as to elevate the dropped voltage level of the boosted voltage. As a result lots of boosted voltage generators should be employed in the memory device.
Referring to FIG. 2, there is illustrated another example block diagram of the core area in the conventional DRAM device. In this example, the supply voltage VDD is used as the equalization signal BLEQ, i.e., inputted to an equalization signal (BLEQ) driver 16′. The boosted voltage VPP is only used at the WL driver 26 transmitting VCORE and the SA controller 24 and it is enough to use the equalization signal BLEQ which has a voltage level higher than (½VCORE+Vt). However, if applying the conventional bit line precharging scheme using the supply voltage VDD to the low power memory device, there occurs speed delay by a relatively boosted back bias and a lowered supply voltage, resulting in deteriorating a time constant tRP relating to a precharge time. That is, in case of using the supply voltage VDD as the BLEQ signal, since a time required in adjusting voltage level of relating circuits to a precharge voltage VBLP becomes longer, it is difficult to set the relating circuits with the precharge voltage VBLP before a next active time tRP. As a result, the possibility of a precharge operation to be failed becomes higher.